Identifying Common Substructure for Incremental Methods

In this paper we solve the problem of identifying a “matching” between two logic circuits or “networks”. A matching is a functions that maps each gate or “node” in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present both an exact and a heuristic way to solve the maximal matching problem. The matching problem does not require any input correspondences; the purpose is to identify structurally identical regions in the networks. We apply this solution to the problem of incremental design. Logic design is usually an iterative process where errors are corrected and optimizations performed repeatedly. A designer rectifies, re-optimizes, and rechecks a design many times. In practice, it is common for small, incremental changes to be made to the design, rather than changing the entirety of the design. Currently, each time the system is modified, the entire set of computations (synthesis,verification) are repeated from the beginning. This results in unnecessary re-computation of information, which can be avoided by re-using results of a previous iteration and information about changes to the system. Synthesis and verification tools that recognize these sequences of slightlydiffering inputs may be able to outperform their counterparts that discard all previous work. This work is concerned with detecting what information has changed in a design, and what information may be re-utilized.